1. Field of the Invention
This invention relates to a latching circuit for latching a logic input level at its output in response to a control signal.
2. Description of the Prior Art
A latching circuit for latching a logic input level at its output in response to a control signal is known. In such a latching circuit, reduction of the number of elements included therein and high speed are required. Particularly, in the microprocessor including such latching circuits, this requirement has been grown increasingly because the operation speed of the latching circuit largely affects the operation speed of the microprocessor.
FIG. 6 is a schematic circuit diagram of a prior art latching circuit. This latching circuit is used with other logic circuit connected to its input and holds the logic level of the logic circuit at its output in response to a control signal. In FIG. 6, numeral 10 is a sample of a logic circuit, that is, a NOR gate which has two inputs and outputs a NOR logic output through NOR operation in accordance with logic levels of its inputs 60 and 70. Numeral 100 is a prior art latching circuit comprising a switching element 101, inverters 102 and 103, a tri-state inverter 104. The switching element 101 and the inverter 104 are controlled in accordance with a logic level of the control signal 90. The switching element 101 is closed when the control signal 90 is logic H. The tri-state inverter 104 is in a conduction state and outputs an inverted signal when the control signal 90 is logic L. The latching circuit 100 receives the output of the NOR gate 10 and outputs a latched signal at its output 180.
Operation of the prior art latching circuit will be described.
Given inputs are inputted into first and second inputs 60 and 70 of the NOR gate 10. The NOR gate 10 outputs a NOR logic output which is sent to the latching circuit 100. When the control signal 90 is logic H, the switching element 101 is in a conduction state, on the other hand, the tri-state inverter 104 is open. Therefore, the inputted NOR logic output is outputted at the output 180 through the switching element 101 and the inverters 102 and 103. When transition of the control signal 90 from logic H to logic L, the switching element 101 turns to a open state and the tri-state inverter 104 turns to a conduction state, so that the inverter 102 and the tri-state inverter 104 form a loop. Therefor, a bistable circuit is established. The bistable circuit maintains a level inputted therein just before transition of the control signal 90 from logic H to logic L. The maintained level at the output of the inverter 102 is outputted through the inverter 103. That is, the latching circuit 100 performs a latching operation such that it latches the output of the NOR gate 10 at its output 180 in accordance with the logic level of the control signal 90.
In the prior art latching circuit, because the latching circuit 100 is connected to the output of the logic circuit, there is a problem of decrease in operation speed due to increase in the number of circuits through which the logic signal passes. Moreover, there is also a problem of increase in the structural elements of the total circuit including the logic circuit and the latching circuit connected to the logic circuit.